seiko epson corporation 1 pf647-05 E0C624A 4-bit single chip microcomputer l core cpu architecture l dot matrix lcd driver l programmable svd circuit/sound generator n description the E0C624A is an advanced single-chip cmos 4-bit microcomputer consisting of the e0c6200 4-bit core cpu. the chip contains the rom, ram, dot matrix lcd driver, programmable svd circuit, time base counter and clock synchronous serial port. interfacing with the external memory, the E0C624A can be applied to any system requiring large memory such as schedule reminder, and dot matrix display function. n features l cmos lsi 4-bit parallel processing l clock ..................................................... 32.768khz/2mhz (max.) (selectable by software) l instruction set ........................................ 108 instructions l instruction cycle time ............................ 153sec, 214sec or 366sec at 32khz (depending on instruction) 5sec, 7sec or 12sec at 1mhz (depending on instruction) l rom capacity ....................................... 6,144 12 bits l ram capacity ........................................ 640 4 bits l external memory capacity .................... read/write 512k bits (max.) read only 1m bits (max.) l input port ............................................... 8 bits (pull-up resistors are available by mask option) l output port ............................................ 20 bits (clock output or buzzer output is available by mask option) l i/o port .................................................. 16 bits (pull-up resistors are available by mask option) l serial i/o port ........................................ 1 port (clock sync.) l dot matrix lcd driver ........................... 40 segments 8 commons/40 segments 16 commons (1/8 or 1/16 duty is selectable by mask option) l built-in svd circuit ................................ 2.3v/2.6v/3.3v/4.5v programmable l built-in stopwatch timer l built-in watchdog timer l built-in time base counter ..................... 3 lines l interrupts ............................................... external : input interrupt 2 lines internal : t imer interrupt 3 lines serial i/o interrupt 1 line l built-in sound generator ........................ with digital envelope (8 sounds programmable) l supply voltage ...................................... 2.2v to 5.5v l current consumption ............................ halt mode (32khz) : 2 .5a (typ.) operating mode (1mhz) : 400a (typ.) l package ................................................ qfp5-128pin (plastic) die form wide voltage operation products http://
2 E0C624A n block diagram n pin configuration k00~03, k10~13 test sin sout sclk p00~03, p10~13, p20~23, p30~33 r00~03, r10~13, r20~23, r30~33, r40~43 v dd v ss v s1 ca~cf v l1~5 seg0~39 com0~15 osc1 osc2 osc3 osc4 v ref reset system reset control rom 6,144 words x 12 bits core cpu e0c6200 output port sound generator svd power controller ram 640 words x 4 bits lcd driver osc stop watch programmable timer input port serial interface interrupt generator timer i/o port 65 102 39 64 index 38 1 128 103 E0C624A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v l3 v l4 v l5 cf n.c. ce cd cc cb ca com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 seg39 seg38 seg37 seg36 seg35 seg34 no. pin name 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 seg33 n.c. seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 no. pin name 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 seg2 seg1 seg0 sclk n.c. sout sin k13 k12 k11 k10 k03 k02 k01 k00 p33 p32 p31 p30 p23 p22 p21 p20 p13 p12 p11 p10 p03 p02 p01 p00 r43 n.c. = no connection no. pin name 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 r42 n.c. r41 r40 r33 r32 r31 r30 r23 r22 r21 r20 r13 r12 r11 r10 r03 r02 r01 r00 v ss reset test osc4 osc3 v s1 osc2 osc1 v dd v ref v l1 v l2 no. pin name qfp5-128pin
3 E0C624A n pin description n basic external connection diagram cf ce cd cc cb ca c3 c2 c1 c7 c6 c5 c4 c8 v rcr cgc cdc ceramic rfc osc4 osc3 osc2 osc1 buzzer v test reset vss dd v r43 r40 + n.c. r00~r03 r10~r13 r20~r23 r30 r31 r32 sin sout sclk lcd panel 120 x 16 com0~com15 seg0~seg39 p00~p03 p10~p13 E0C624A serial device key matrix 8 x 6 x'tal rfx cgx r41 r42 r33 k00~k03 k10~k13 p22~p23 p30~p33 power 5v vss v v2 v3 v5 cl fr res rd wr cs a0 a0~a12 d0~d7 cs1 we cs2 oe vss v srm2064 sed1521f aa db0~db7 seg0~seg79 ref s1 v l1 v l2 v l3 v l4 v l5 dd dd p20 p21 x'tal rfx cgx ceramic rfc cgc cdc rcr c1~c3 c4 c5 c6 c7 c8 crystal oscillator feedback resistor trimmer capacitor ceramic oscillator feedback resistor gate capacitance drein capacitance resistance for cr oscillation voltage booster capacitor (1)~(3) capacitor between v dd and v l1 capacitor between v dd and v l2 capacitor between v dd and v l4 capacitor between v dd and v l5 capacitor between v dd and v s1 32.768khz ci(max.)=35k w 10m w 5~25pf 500khz~2mhz 1m w 100pf 100pf 20k w ~100k w 0.1 f * 1 0.1 f * 1 0.1 f * 1 0.1 f * 1 0.1 f * 1 0.1 f note: ? s i nce srm2064 is applied in the external sram in this example, the power supply voltage of 5 v is used. ? the above table is simply an example, and is not guaranteed to work. v dd v ss v s1 v l1 ? l5 v ref ca?f osc1 osc2 osc3 osc4 k00?03, k10?13 p00?03, p10?13 p20?23 p30?33 r00?03, r10?13 r20?23, r30 r31 r32 r33 r40 r41 r42 r43 sin sout sclk seg0?9 com0?5 reset test pin name i i o i o i o i i/o i/o i/o o o o o o o o o i o i/o o o i i in/out power source (+) terminal power source (-) terminal oscillation and internal logic system regulated voltage lcd system power (1/4 or 1/5 bias may be selected by mask option) lcd system power test terminal booster capacitor connecting terminal crystal oscillation input terminal crystal oscillation output terminal ceramic or cr oscillation input terminal (selected by mask option) ceramic or cr oscillation output terminal (selected by mask option) input terminal (use of pull up resistor is selected by mask option) i/o terminal (setting for data bus may be selected by mask option) i/o terminal (cs output may be selected by mask option) i/o terminal output terminal (setting for address bus may be selected by mask option) output terminal (dc, address or wr output may be selected by mask option) output terminal (dc or rd output may be selected by mask option) output terminal (dc or srdy output may be selected by mask option) output terminal (dc, cl or fout output may be selected by mask option) output terminal (dc or fr output may be selected by mask option) output terminal (dc, bz or fout output may be selected by mask option) output terminal (dc or bz output may be selected by mask option) serial interface input terminal serial interface output terminal serial interface clock input/output terminal lcd segment output terminal lcd common output terminal initial reset input terminal test input terminal 125 117 122 127, 128, 1? 126 10?, 4 124 123 121 120 79?2 95?8 87?4 83?0 116?04 103 102 101 100 99 97 96 71 70 68 67?5, 33?7 11?6 118 119 pin no. function * 1 when the load on the liquid crystal system is large, increase the capacitance of the voltage booster capacitors (c1Cc3) and the capacitors between v dd and liquid crystal system power (c4Cc7).
4 E0C624A l dc characteristics unit v v v v a a a ma ma ma ma a a a a (unless otherwise specified: v dd =0v,v ss =-3.0v,v l1 =-1.0v,v l2 =-2.0v,v l4 =-3.0v,v l5 =-4.0v,f osc1 =32.768khz,f osc3 =1mhz,ta=25 c,c1?8=0.047 f) max. 0 0.8? ss 0 v ss +0.2 0.5 -15 0 -1.0 -2.0 -30 -10 typ. min. 0.2? ss v ss -0.2 v ss 0 -45 -0.5 4.0 8.0 30 10 characteristic high level input voltage low level input voltage high level input voltage low level input voltage high level input current low level input current (1) low level input current (2) high level output current (1) low level output current (1) high level output current (2) low level output current (2) common output current segment output current symbol v hin v lin v hin v lin i ih i il1 i il2 i oh1 i ol1 i oh2 i ol2 i oh3 i ol3 i oh4 i ol4 v ss =-2.2 to -5.5v ta=25 c v ss =-2.2 to -5.5v ta=25 c v ss =-3.0v v ih =0v v ss =-3.0v v il1 =v ss with pull-up resistor v ss =-3.0v v il2 =v ss no pull-up resistor v ss =-2.2v v oh1 =-0.5v v ss =-2.2v v ol1 =v ss +0.5v v ss =-2.2v v oh2 =-0.5v v ss =-2.2v v ol1 =v ss +0.5v v oh3 =-0.05v v ol3 =v l5 +0.05v v oh4 =-0.05v v ol4 =v l5 +0.05v condition k00?3?0?3, p00?3?0?3 p20?23?0?3, sin, sclk reset k00?3?0?3, p00?3?0?3 p20?23?0?3, sin, sclk reset k00?3?0?3, p00?3?0?3 p20?23?0?3, sin, sclk reset k00?3?0?3, p00?3?0?3 p20?23?0?3, sin, sclk reset p00?3?0?3?0?3?0?3 r00?3?0?3?0?3?0?3 r40?1, sout, sclk p00?3?0?3?0?3?0?3 r00?3?0?3?0?3?0?3 r40?1, sout, sclk r42?3 r42?3 com0?5 seg0?9 n electrical characteristics l absolute maximum ratings rating supply voltage input voltage (1) input voltage (2) operating temperature storage temperature soldering temperature / time permissible dissipation * 1 * 1: in case of plastic package (qfp5-128pin). symbol v ss v i v iosc topr tstg tsol p d value -7.0 to 0.5 v ss - 0.3 to 0.5 v s1 - 0.3 to 0.5 -20 to 70 -65 to 150 260 c, 10sec (lead section) 250 unit v v v c c mw (v dd =0v) l recommended operating conditions condition supply voltage oscillation frequency (1) oscillation frequency (2) oscillation frequency (3) voltage booster capacitor (1) voltage booster capacitor (2) voltage booster capacitor (3) capacitor between v dd and v l1 capacitor between v dd and v l2 capacitor between v dd and v l4 capacitor between v dd and v l5 capacitor between v dd and v s1 symbol v ss f osc1 f osc3 f osc3 c1 c2 c3 c4 c5 c6 c7 c8 remark v dd =0v vsc="0" vsc="1" vsc="2" vsc="1" vsc="2" unit v v v khz khz khz f f f f f f f f (ta=-20 to 70 c) max. -1.8 -2.2 -3.5 50 1,200 2,300 typ. -3.0 -3.0 -3.0 32.768 1,000 2,000 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 min. -3.8 -5.5 -5.5 20 50 50
5 E0C624A l analog circuit characteristics and current consumption * 1: * 2: * 3: svd circuit: off status, vsc = "0", osc1: oscillating with crystal, oscc= "0" svd circuit: off status, vsc = "1", osc1: oscillating with crystal svd circuit: off status, vsc = "2", osc1: oscillating with crystal, v ss = -5.0v unit v v v v v v v v v v v v s a a a a (unless otherwise specified: v dd =0v,v ss =-3.0v,v l1 =-1.0v,v l2 =-2.0v,v l4 =-3.0v,v l5 =-4.0v,f osc1 =32.768khz,f osc3 =1mhz,ta=25 c,c1?8=0.047 f) max. 1/2? l2 0.95 typ. 0.88 3/2? l2 0.95 2? l2 0.95 typ. 0.88 2? l1 0.90 3? l1 0.90 4? l1 0.90 -2.05 -2.30 -2.90 -3.90 100 5.0 9.0 600 1,500 typ. -1.80 -1.85 -1.90 -1.95 -2.01 -2.06 -2.11 -2.17 -2.22 -2.27 -2.32 -2.38 -2.43 -2.48 -2.53 -2.59 -0.92 -0.95 -0.97 -1.00 -1.03 -1.05 -1.08 -1.11 -1.13 -1.16 -1.18 -1.21 -1.24 -1.26 -1.29 -1.32 -2.20 -2.50 -3.10 -4.20 2.5 6.5 400 1,000 min. 1/2? l2 -0.1 typ. 1.12 3/2? l2 2? l2 typ. 1.12 2? l1 3? l1 4? l1 -2.35 -2.70 -3.30 -4.50 characteristic liquid crystal drive voltage (normal mode) liquid crystal drive voltage (heavy load protection mode) svd voltage svd circuit response time current consumption symbol v l1 v l2 v l4 v l5 v l1 v l2 v l4 v l5 v svd0 v svd1 v svd2 v svd3 t svd i hlt i ex1 i ex2 i ex3 condition connect 1m w load resistor between v dd and v l1 (no panel load) connect 1m w load resistor between v dd and v l2 (no panel load) connect 1m w load resistor between v dd and v l4 (no panel load) connect 1m w load resistor between v dd and v l5 (no panel load) connect 1m w load resistor between v dd and v l1 (no panel load) connect 1m w load resistor between v dd and v l2 (no panel load) connect 1m w load resistor between v dd and v l4 (no panel load) connect 1m w load resistor between v dd and v l5 (no panel load) svc="0" svc="1" svc="2" svc="3" during halt during operation at 32khz during operation at 1mhz during operation at 2mhz no panel load * 1 no panel load * 2 no panel load * 3 lc="0" lc="1" lc="2" lc="3" lc="4" lc="5" lc="6" lc="7" lc="8" lc="9" lc="10" lc="11" lc="12" lc="13" lc="14" lc="15" lc="0" lc="1" lc="2" lc="3" lc="4" lc="5" lc="6" lc="7" lc="8" lc="9" lc="10" lc="11" lc="12" lc="13" lc="14" lc="15"
6 E0C624A l oscillation characteristics the oscillation characteristics change depending on the conditions (components used, board pattern, etc.). use the follow- ing characteristics as reference values. osc1 crystal oscillation circuit unit sec pf pf ppm ppm ppm v m w (unless otherwise specified: v dd =0v, v ss =-3.0v, crystal: c-002r (c i =35k w ), c gx =25pf, c dx =built-in, r fx =10m w , vsc="0", ta=25 c) max. 5 5 10 -5.5 typ. 22 21 45 min. -10 35 200 characteristic oscillation start time built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol t sta c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition v ss =-2.2 to -5.5v package as assembled bare chip v ss =-2.2 to -5.5v c g =5 to 25pf c g =5pf between osc1 and v dd , v s1 osc3 cr oscillation circuit (1) osc3 cr oscillation circuit (2) unit ms % khz (unless otherwise specified: v dd =0v, v ss =-3.0v, vsc="1", ta=25 c) max. 3 5 860 130% typ. 860 min. -5 860 70% characteristic oscillation start time frequency/voltage deviation oscillation frequency symbol t sta ? f/ ? v f cr condition v ss =-2.2 to -5.5v v ss =-2.2 to -5.5v r osc =40k w osc3 ceramic oscillation circuit (1) osc3 ceramic oscillation circuit (2) unit ms % mhz (unless otherwise specified: v dd =0v, v ss =-5.0v, vsc="2", ta=25 c) max. 3 5 1.7 130% typ. 1.7 min. -5 1.7 70% characteristic oscillation start time frequency/voltage deviation oscillation frequency symbol t sta ? f/ ? v f cr condition v ss =-3.5 to -5.5v v ss =-3.5 to -5.5v r osc =20k w unit ms % (unless otherwise specified: v dd =0v, v ss =-3.0v, vsc="1", ceramic: csb 1000j (murata mfg. co.), c gc =c dc =100pf, r fc =1m w , ta=25 c) max. 3 3 typ. min. -3 characteristic oscillation start time frequency/voltage deviation symbol t sta ? f/ ? v condition v ss =-2.2 to -5.5v v ss =-2.2 to -5.5v unit ms % (unless otherwise specified: v dd =0v, v ss =-5.0v, vsc="2", ceramic: csa 2.00mg (murata mfg. co.), c gc =c dc =100pf, r fc =1m w , ta=25 c) max. 3 3 typ. min. -3 characteristic oscillation start time frequency/voltage deviation symbol t sta ? f/ ? v condition v ss =-3.5 to -5.5v v ss =-3.5 to -5.5v
E0C624A notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 1999 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 20 0.1 23.6 0.4 65 102 14 0.1 17.6 0.4 39 64 index 0.2 0.05 38 1 128 103 2.7 0.1 0.1 3 max 1.8 0.8 0.2 0 10 0.15 0.05 0.5 n package dimensions plastic qfp5-128pin unit: mm
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